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ir3514 page 1 of 46 10/30/2007 data sheet xphase3 tm amd hybrid control ic description the ir3514 hybrid control ic combined with xphase3 tm phase ics provides a full featured and flexible way to implement a complete amd svid or pvid power solution. it has the ability to independently contr ol both the vdd core and vddnb auxiliary planes requir ed by the cpu when operated in svi (serial vid interface) mode. the ir3514 can also receive power savings commands through the svi serial bus and communicate this information to the ir3507 or other phase ics with psi input capabilities. when opera ted in pvi (parallel vid interface) mode, the ir3514 co ntrols the vdd core plane through 6 parallel vid bi ts and the vddnb auxiliary plane power stage goes to h igh impedance. pvi/svi selection is made by sampling vid1 input upon enable. the ir3514 interf aces with any number of phase ics each driving and monitoring a single phase. the xphase3 tm architecture results in a power supply that is sma ller, less expensive, and easier to design while providing hig her efficiency than conventional approaches. features x in svi mode (vid1=0 upon enable) o 2 converter outputs for the amd processor vdd core and vddnb auxiliary planes o amd serial vid interface independently programs bo th output voltages and operation o both converter outputs boot to 2-bit boot vid co des which are read and stored from the svc & svd parallel inputs upon the assertion of the ena ble input o pwrok input signal activates svid after successful boot start-up o both converter outputs can be independently turned on and off through svid commands o deassertion of pwrok prior to enable causes the co nverter output to transition to the stored pre-pwrok vid codes o connecting the pwrok input to vccl disables svid a nd implements vfix mode with both output voltages programmed via svc & svd parallel i nputs per the 2 bit vfix vid codes o psi_l commands are forwarded to vdd core phase ics x in pvi mode (vid1=1 upon enable) o single converter control for vdd with the vddnb po wer stage in a high impedance state o amd 6 bit parallel vid programs the vdd regulation voltage x vrrdy monitors output voltages, vrrdy will deasser t if any output voltage is out of spec x 0.5% overall system set point accuracy x programmable dynamic vid slew rates x programmable vid offset (vdd output only) x programmable output impedance (vdd output only) x high speed error amplifiers with wide bandwidths o f 30mhz and fast slew rates of 12v/us x remote sense amplifiers provide differential sensi ng and require less than 50ua bias current x programmable per phase switching frequency of 250k hz to 1.5mhz x daisy-chain digital phase timing provides accurate phase interleaving without external components x hiccup over current protection with delay during n ormal operation x central over voltage detection and communication t o phase ics through the iin (ishare) pin x ovp disabled during dynamic vid down transitions t o prevent false triggering x detection and protection of open remote sense line s x gate drive and ic bias linear regulator control wi th programmable output voltage and uvlo x simplified vr ready output provides indication of proper operation and avoids false triggering x thermally enhanced 40l mlpq (6mm x 6mm) package x over voltage signal to system with over voltage de tection during powerup and normal operation downloaded from: http:///
ir3514 page 2 of 46 10/30/2007 ordering information device package order quantity IR3514MTRPBF 40 lead mlpq (6 x 6 mm body) 3000 per reel * ir3514mpbf 40 lead mlpq (6 x 6 mm body) 100 piece strips * samples only application circuit figure 1 C ir3514 application circuit downloaded from: http:///
ir3514 page 3 of 46 10/30/2007 pin description pin# pin symbol pin description 1-3 vid0, vid5, vid4 pvi vid inputs (ignored in svi mode). requires an external pull-up bias and should not be floated 4 pwrok svi system wide power good signal and input to the ir3514. when asserted, the ir3514 output voltage is programmed through the svid interface protocol. connecting this pin to vccl enables vfix mode upon enable. ignored in pvi. 5 enable enable input. a logic low applied to this pin puts the ic into fault mode. in svi mode, a logic high on the pin enables the converter and stores the svc and svd input states to determine either a 2-bit boot o r vfix vid, depending on the state of pwrok. do not float this pin as the lo gic state will be undefined. 6 iin2 svi mode output 2 average current informatio n input from the phase ic(s). this pin also communicates an over voltage condition to the output 2 phase ics. 7 ss/del2 in svi mode, programs the output 2 startu p and over current protection delay timing. connect an external capacitor to lgnd to pr ogram. 8 vdac2 svi mode output 2 reference voltage program med by svid commands. connect an external rc network to lgnd to program the dynam ic vid slew rate and provide compensation for the internal buffer amplif ier. in pvi mode, vdac2 is forced to 500mv. 9 ocset2 programs the svi mode output 2 hiccup over -current threshold with an external resistor to vdac2 and an internal rosc based curren t source. over-current protection can be disabled by setting an over-curre nt threshold higher than the maximum possible signal on the iin2 pin from the ph ase ics; do not exceed 5v or float this pin as improper operation will occur. 10 eaout2 svi mode error amplifier 2 output. held low in pvi mode. 11 nc no connection 12 fb2 inverting input to error amplifier 2. 13 vout2 output 2 remote sense amplifier output. 14 vosen2+ output 2 remote sense amplifier input. k elvin at the load. 15 vosen2- output 2 remote sense amplifier input. k elvin at the load return. 16 vosen1- output 1 remote sense amplifier input. kelvin at the load return. 17 vosen1+ output 1 remote sense amplifier input. kelvin at the load. 18 vout1 output 1 remote sense amplifier output. 19 fb1 inverting input to error amplifier 1. conve rter output voltage can be programmed above the vdac1 voltage by connecting an external resistor in series with this pin. there is an rosc based curre nt sink on this pin. 20 nc no connection 21 eaout1 error amplifier 1 output. 22 ocset1 programs the svi mode output 1 hiccup ove r-current threshold with an external resistor to vdac1 and an internal rosc based curren t source. over-current protection can be disabled by setting an over-curre nt threshold higher than the maximum possible signal on the iin2 pin from the ph ase ics, do not exceed 5v or float this pin as improper operation will occur. 23 vdac1 output 1 reference voltage programmed by e ither svid commands or parallel vid bits. connect an external rc network to lgnd to program the dynamic vid slew rate and provide compensation for the internal buffer amplifier. 24 ss/del1 programs the output 1 startup and over c urrent protection delay timing. connect an external capacitor to lgnd to program. 25 iin1 output 1 average current information input from the phase ic(s). this pin also communicates an over voltage condition to the outpu t 1 phase ics. 26 vdrp1 buffered output of the iin1 signal. connec t an external rc network to fb1 to program converter output impedance. downloaded from: http:///
ir3514 page 4 of 46 10/30/2007 pin description continued: pin# pin symbol pin description 27 rosc/ovp connect a resistor to lgnd to program o scillator frequency and ocset1, ocset2, fb1, vdac1, and vdac2 bias currents. oscill ator frequency equals switching frequency per phase. the pin voltage is 0 .6v during normal operation and higher than 1.6v if over-voltage condition is d etected. 28 psi_l digital output to communicate psi_l to pha se ics. 29 lgnd local ground for internal circuitry and ic substrate connection 30 nc no connection 31 clkout clock output at switching frequency multi plied by phase number. connect to clkin pins of phase ics. 32 phsout phase clock output at switching frequency per phase. connect to phsin pin of the first phase ic. 33 phsin feedback input of phase clock. connect to phsout pin of the last phase ic. 34 vccl output of the voltage regulator, and power input for clock oscillator circuitry. connect a decoupling capacitor to lgnd. 35 vcclfb non-inverting input of the voltage regula tor error amplifier. output voltage of the regulator is programmed by a resistor divider conne cted to vccl. 36 vccldrv output of the vccl regulator error ampli fier to control an external pass transistor. the pin senses 12v power supply through a resistor. 37 vrrdy open collector output. it is asserted in svi mode when both outputs are regulated. it is asserted in pvi mode when vdd out put is regulated. connect external pull-up. 38 svc/vid3 in svi mode, svc (serial vid clock) is an input to ir3514 that is driven by an open drain output of the processor. in pvi mode, t his pin functions as the vid3 input. it requires an external pull-up and should n ot be floated. 39 svd/vid2 in svi mode, svd (serial vid data) is a bidirectional signal that is an input and open drain output for both the amd processor and th e ir3514. in pvi mode, this pin functions as the vid2. it requires an external pull-up and should not be floated. 40 vid1 this pin determines the control mode of the ir3514, either svi or pvi. svi mode is selected if vid1=0 upon enable. pvi mode i s selected if vid1=1 upon enable. it requires an external pull-up and should not be floated. downloaded from: http:///
ir3514 page 5 of 46 10/30/2007 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltages are absolute voltages referenced to th e lgnd pin. operating junction temperature..0 to 150 o c storage temperature range.-65 o c to 150 o c esd ratinghbm class 1c jedec standard msl rating2 reflow temperature.260 o c pin # pin name v max v min i source i sink 1 vid0 8v -0.3v 1ma 1ma 2 vid5 8v -0.3v 1ma 1ma 3 vid4 8v -0.3v 1ma 1ma 4 pwrok 8v -0.3v 1ma 1ma 5 enable 3.5v -0.3v 1ma 1ma 6 iin2 8v -0.3v 5ma 1ma 7 ss/del2 8v -0.3v 1ma 1ma 8 vdac2 3.5v -0.3v 1ma 1ma 9 ocset2 8v -0.3v 1ma 1ma 10 eaout2 8v -0.3v 25ma 10ma 12 fb2 8v -0.3v 1ma 1ma 13 vout2 8v -0.3v 5ma 25ma 14 vosen2+ 8v -0.5v 5ma 1ma 15 vosen2- 1.0v -0.5v 5ma 1ma 16 vosen1- 1.0v -0.5v 5ma 1ma 17 vosen1+ 8v -0.5v 5ma 1ma 18 vout1 8v -0.3v 5ma 25ma 19 fb1 8v -0.3v 1ma 1ma 21 eaout1 8v -0.3v 25ma 10ma 22 ocset1 8v -0.3v 1ma 1ma 23 vdac1 3.5v -0.3v 1ma 1ma 24 ss/del1 8v -0.3v 1ma 1ma 25 iin1 8v -0.3v 5ma 1ma 26 vdrp1 8v -0.3v 35ma 1ma 27 rosc/ovp 8v -0.3v 1ma 1ma 28 psi_l 8v -0.3v 1ma 10ma 29 lgnd n/a n/a 20ma 1ma 31 clkout 8v -0.3v 100ma 100ma 32 phsout 8v -0.3v 10ma 10ma 33 phsin 8v -0.3v 1ma 1ma 34 vccl 8v -0.3v 1ma 20ma 35 vcclfb 3.5v -0.3v 1ma 1ma 36 vccldrv 10v -0.3v 1ma 50ma 37 vrrdy 8v -0.3v 1ma 20ma 38 svc/vid3 8v -0.3v 1ma 1ma 39 svd/vid2 8v -0.3v 1ma 10ma 40 vid1 8v -0.3v 1ma 1ma downloaded from: http:///
ir3514 page 6 of 46 10/30/2007 recommended operating conditions for reliable opera tion with margin 4.75v ? vccl ? 7.5v, -0.3v ? vosen-x ? 0.3v, 0 o c ? t j ? 100 o &n ? r osc ?n , c ss/delx = 0.1uf electrical characteristics the electrical characteristics involve the spread o f values guaranteed within the recommended operatin g conditions (unless otherwise specified). typical va lues represent the median values, which are related to 25c. ir3514 electrical characteristics ir3514 electrical characteristics parameter test condition min typ max unit pvid interface vidx input threshold 0.85 0.95 1.05 v vidx pull-down resistance 100 175 250 n psi_l output output voltage i(psi_l) = 3ma 150 300 mv pull-up resistance (to vccl) 6 10 20 n parameter test condition min typ max unit svid interface threshold increasing 0.850 0.950 1.05 v threshold decreasing 550 650 750 mv svc & svd input thresholds threshold hysteresis 195 300 405 mv bias current 0v ?9[?969'qrwdvvhuwhg -5 0 5 ua svd low voltage i(svd)= 3ma 20 300 mv svd output fall time 0.7 x vdd to 0.3 x vdd, 1.425v ?9''? 1.9v, 10 pf ?&e?s) cb=capacitance of one bus line (note 1) 20+ 0.1 xcb(pf) 250 ns pulse width of spikes suppressed by the input filter note 1 97 260 410 ns oscillator phsout frequency -10% see figure 2 +10% khz rosc voltage 0.57 0.600 0.630 v clkout high voltage i(clkout)= -10 ma, measure v(vc cl) C v(clkout). 1 v clkout low voltage i(clkout)= 10 ma 1 v phsout high voltage i(phsout)= -1 ma, measure v(vcc l) C v(phsout) 1 v phsout low voltage i(phsout)= 1 ma 1 v phsin threshold voltage compare to v(vccl) 30 50 70 % vdrp1 buffer amplifier input offset voltage v(vdrp1)C v(iin1), 0.5v ?9,,1 1) ?9 -8 0 8 mv source current 0.5v ?9,,1 1) ?9 2 30 ma sink current 0.5v ?9,,1 1) ?9 0.2 0.4 0.6 ma unity gain bandwidth note 1 8 mhz slew rate note 1 4.7 v/ p s iin bias current -1 0 1 p a downloaded from: http:///
ir3514 page 7 of 46 10/30/2007 parameter test condition min typ max unit remote sense differential amplifiers unity gain bandwidth note 1 3.0 6.4 9.0 mhz input offset voltage 0.5v ?9926(1[ - v(vosenx-) ?9 note 2 -3 0 3 mv source current 0.5v ?9926(1[ - v(vosenx-) ?9 0.5 1 1.7 ma sink current 0.5v ?9926(1[ - v(vosenx-) ?9 2 12 18 ma slew rate 0.5v ?9926(1[ - v(vosenx-) ?9 , note 1 2 4 8 v/us vosen+ bias current 0.5v < v(vosenx+) < 1.6v 30 50 ua vosen- bias current -0.3v ?926(1 x- ?9$oo9,'&rghv 30 50 ua vosen+ input voltage range v(vccl)=7v 5.5 v low voltage v(vccl) =7v 250 mv high voltage v(vccl) C v(voutx) 0.5 1 v soft start and delay start delay measure enable to eaoutx activation 1 2.9 3.5 ms start-up time measure enable activation to vrrdy 3 8 13 ms oc delay time v(iinx) C v(ocsetx) = 500 mv 300 650 1000 us ss/delx to fbx input offset voltage with fbx = 0v, adjust v(ss/delx) until eaoutx drives high 0.7 1.4 1.9 v charge current -30 -50 -70 p a oc delay/vid off discharge currents note 1 30 47 70 p a fault discharge current 2.5 4.5 6.5 p a hiccup duty cycle i(fault) / i(charge) 8 10 12 ua/ ua charge voltage 3.5 3.9 4.2 v delay comparator threshold relative to charge volta ge, ss/delx rising note 1 80 mv delay comparator threshold relative to charge volta ge, ss/delx falling note 1 120 mv delay comparator hysteresis note 1 40 mv discharge comp. threshold 150 200 300 mv over-current comparators input offset voltage 1v ?92&6(7[?9 -35 0 35 mv ocset bias current -5% vrosc(v)*1000 ????????? ? ? +5% p a 2048-4096 count threshold adjust rosc value to find threshold 11.4 n 1024-2048 count threshold adjust rosc value to find threshold 32.5 n error amplifiers vid ?9 -0.5 0.5 % 0.8v ?9,'9 -5 +5 mv system set-point accuracy (deviation from table 1, 2, and 3 per test circuit in figures 2a & 2b) 0.5v ?9,'9 -8 +8 mv input offset voltage measure v(fbx) C v(vdacx)). n ote 2 25 o c ? t j ? 100 o c -1 0 1 mv fb1 bias current -5% vrosc(v)*1000 ????????? ? ? +5% p a fb2 bias current -1 0 1 p a dc gain note 1 100 110 120 db bandwidth note 1 20 30 40 mhz slew rate note 1 7 12 20 v/ p s sink current 0.4 0.85 1 ma source current 5.0 8.5 12.0 ma maximum voltage measure v(vccl) C v(eaoutx) 500 780 950 mv downloaded from: http:///
ir3514 page 8 of 46 10/30/2007 parameter test condition min typ max unit minimum voltage 120 250 mv open voltage loop detection threshold measure v(vccl) - v(eaout), relative to error amplifier maximum voltage. 125 300 600 mv open voltage loop detection delay measure phsout pulse numbers from v(eaoutx) = v(vccl) to vrrdy = low. 8 pulses enable input blanking time noise pulse < 100ns will not register an enable state change. note 1 75 250 400 ns vdac references source currents includes i(ocsetx) -8% 3000*vrosc(v) ?????????? ? ? +8% p a sink currents includes i(ocsetx) -11% 1000*vrosc(v) / ????????? ? ? +11% p a vrrdy output under voltage threshold - voutx decreasing reference to vdacx -365 -315 -265 mv under voltage threshold - voutx increasing reference to vdacx -325 -275 -225 mv under voltage threshold hysteresis 5 53 110 mv output voltage i(vrrdy) = 4ma 150 300 mv leakage current v(vrrdy) = 5.5v 0 10 p a vccl activation threshold i(vrrdy) = 4ma, v(vrrdy) = 300mv 1.73 3.5 v over voltage protection (ovp) comparators threshold at power-up 1.60 1.73 1.83 v voutx threshold voltage compare to v(vdacx) 100 12 5 150 mv ovp release voltage during normal operation compare to v(vdacx) -13 3 20 mv threshold during dynamic vid down 1.66 1.72 1.78 v dynamic vid detect comparator threshold 25 50 75 mv propagation delay to iin measure time from v(voutx) > v(vdacx) (250mv overdrive) to v(iinx) transition to > 0.9 * v(vccl). 90 180 ns ovp high voltage measure v(vccl)-v(rosc/ovp) 0 1.2 v ovp power-up high voltage v(vccldrv)=1.8v. measure v(vccl)- v(rosc/ovp) 0 0.2 v propagation delay to ovp measure time from v(voutx) > v(vdacx) (250mv overdrive) to v(rosc/ovp) transition to >1v. 150 300 ns iin pull-up resistance 5 15 open sense line detection sense line detection active comparator threshold voltage 150 200 250 mv sense line detection active comparator offset voltage v(voutx) < [v(vosenx+) C v(lgnd)] / 2 35 62.5 90 mv vosen+ open sense line comparator threshold compare to v(vccl) 86.5 89.0 91.5 % vosen- open sense line comparator threshold 0.36 0.40 0.44 v sense line detection source currents v(voutx) = 100mv 200 500 700 ua downloaded from: http:///
ir3514 page 9 of 46 10/30/2007 note 1: guaranteed by design, but not tested in production note 2: vdacx outputs are trimmed to compensate for error & amp remote sense amp input offsets bold letters: critical specs tbd: to be determined by applications engineer tbs: to be selected by the design engineer to facilitate the ic design parameter test condition min typ max unit vccl regulator amplifier reference feedback voltage 1.15 1.2 1.25 v vcclfb bias current -1 0 1 ua vccldrv sink current 10 30 ma uvlo start threshold compare to v(vccl) 89.0 93.5 9 7.0 % uvlo stop threshold compare to v(vccl) 81.0 85.0 89 .0 % hysteresis compare to v(vccl) 7.0 8.25 9.5 % enable, pwrok inputs threshold increasing 1.38 1.65 1.94 v threshold decreasing 0.8 0.99 1.2 v threshold hysteresis 470 620 770 mv bias current 0v ?9[?969&qrwdvvhuwhg -5 0 5 ua pwrok vfix mode threshold 3.3v (vccl +3.3)(v) / 2 vccl v general vccl supply current 4 10 15 ma downloaded from: http:///
ir3514 page 10 of 46 10/30/2007 phsout frequency vs rrosc chart phsout frequency vs. rrosc 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 5 10 15 20 25 30 35 40 45 50 55 rrosc (kohm) frequency (khz) figure 2 - phsout frequency vs. r rosc chart downloaded from: http:///
ir3514 page 11 of 46 10/30/2007 set dominant uv cleared fault latch1 vid3 + - 25k s r q + - open daisy dis idchg 4.5ua + - vdac2 vosen2- vosen2+ iin2 ocset2 fb2 eaout2 ov1 ss/del1 47ua idchg1 vccl + - vccl 3.9v ss/del cleared fault latch1 vid7 reset dominant power-up ok latch delay comparator set dominant 0.2v discharge comparator 80mv 120mv ivosen- vidsel oc1 after vrrdy ov1 fault latch irosc disable2 open sense1 ichg 50ua over voltage comparator vdac buffer amplifier error amplifier flt1 svid to metal svid to svid metal to svid low to high high to low vid3 vout1 vid on-the-fly high to low dly out1 dly out2 dvid1 vdac2 vout2 vid off uv2 svid enabled vid3 dvid2 vout1 uv comparator vid3 vout1 vid off connection to vccl uv2 + - 275mv 315mv vout2 uv comparator uv1 + - sscl fs2 vdac1 isource remote sense amplifier dly out1 svid to svid 200mv 1.6v 50mv isink 0.4v dynamic vid2 down detect comparator vccl*0.9 ivosen2- ivosen2+ 1.4v soft start clamp 125mv oc limit comparator 4 open sense line detect comparators 60mv iocset open sense line2 sscl fs1 flt2 vccl reset 1.08v vdac1 + - vid3 + - s r q irosc 47ua + - idchg2 sscl fs1 s r q q open control2 + - 25k + - dis vccl + - dis 275mv 315mv + - + - + + - + - svid to metal vid3 25k + - + - uv cleared fault latch2 set dominant + - s r q vccl 25k + - s r q read & store pre-pwrok 2 bit vid sscl fs2 phsout dis dynamic vid1 down detect comparator 8 pulse delay vid3 flt2 flt1 open control loop comparator irosc open daisy phsout dly out1 ovlatch dis idchg 4.5ua vfix mode vid3 oc2 bf vrrdy r d clk q q en r d . q q s vid3 vrrdy svi-s disable psi_l ovlatch pvi-s vccl uvlo + - parallel block phsout clkout irosc lgnd rosc phsin phsout clkout fault phsin vid0 open daisy chain 0.6v rosc buffer amplifier current source generator oc1 bf vrrdy en en detection pulse2 vccl uvlo vccl-uvlo disable oc delay couter irosc dis reset reset vccl - 1.2v ov2 ov1 phsout dis dis ov1_2 oc delay couter irosc dis dis dis phsout ov2 select mode vdd vccl vdac1 dly out2 vrrdy ovlatch svi-s svi-s pvi-s 10k select mode psi_l vid3 vid3/svc vid5 vid4 disable svi-s por vid3 svd dchg2 dly out2 s r q q disable svi (seriel vid interface) 0.86 svc vout1 vid off dchg1 flt1 dchg1 svd dis vout2 vccl disable vccl uvlo vccl uvlo detection pulse1 ov1-2 ov2 ov1 metal to svid + - + - 25k ss/del2 + - + - back to pre-pwrok 2 bit vid enable vrrdy select mode vdrp1 vccldrv vcclfb vccl vosen1- vosen1+ vout1 ocset1 fb1 eaout1 vdac1 vid3 iin1 pvi-s vid7 vccl vccl flt2 vid3 ivosen- vidsel uv1 irosc disable1 irosc pwrok delay comparator set dominant 3.9v ss/del cleared fault latch2 vout2 vid off error amplifier 1.65v 1v enable comparator svi-s vdac buffer amplifier d/a converter vout2 vid on-the-fly high to low vccl regulator amplifier over voltage comparator 250ns blanking vccl uvl comparator 0.94 1.2v isink isource remote sense amplifier vdrp amplifier discharge comparator 80mv 120mv reset dominant power-up ok latch dis 200mv 1.6v 50mv 0.2v 0.4v vccl*0.9 ivosen1- ivosen1+ soft start clamp ifb ov fault latch set dominant oc limit comparator 1.4v vid0 vid2/svd vid1 4 open sense line detect comparators 60mv 125mv flt2 50ua open sense line1 oc2 after vrrdy dis vdac2 iocset ichg en 1.08v en 8 pulse delay detection pulse1 vccl reset + - internal circuit bias + - 25k dchg2 + - vid3 svc vid3 vid3 + - open sense2 + - + - vccl uvlo 25k flt1 + - 25k + - open control loop comparator vccl vid3 + - + + - s r q open control1 detection pulse2 figure 3 C ir3514 block diagram downloaded from: http:///
ir3514 page 12 of 46 10/30/2007 system set point test converter output voltage is determined by the syste m set point voltage which is the voltage that appea rs at the fbx pins when the converter is in regulation. the s et point voltage includes error terms for the vdac digital-to- analog converters, error amp input offsets, and rem ote sense input offsets. the voltage appearing at t he vdacx pins is not the system set point voltage. system set point vol tage test circuits for outputs 1 and 2 are shown in figures 4a and 4b. cvdac1 + - + - rrosc + - rvdac1 rocset1 + - eaout1 fb1 ocset1 vdac1 vosen1- vosen1+ vout1 lgnd rosc irosc irosc eaout vosns- vdac1 buffer amplifier ifb1 rosc buffer amplifier 1.2v "fast" vdac isink isource ir3514 system set point voltage iocset1 current source generator remote sense amplifier error amplifier irosc figure 4a - output 1 system set point test circuit cvdac2 + - + - rrosc + - rvdac2 rocset2 + - vdac2 ocset2 fb2 eaout2 lgnd vout2 vosen2+ vosen2- irosc rosc vosns- eaout vdac2 buffer amplifier "fast" vdac 1.2v rosc buffer amplifier system set point voltage ir3514 isource isink irosc error amplifier remote sense amplifier current source generator iocset2 figure 4b - output 2 system set point test circuit downloaded from: http:///
ir3514 page 13 of 46 10/30/2007 system theory of operation pwm control method the pwm block diagram of the xphase3 tm architecture is shown in figure 5. feed-forward vo ltage mode control with trailing edge modulation is used. a high-gain wide-bandwidth voltage type error amplifier in the control ic is used for the voltage control loop. input voltage is sensed in phase ics and feed-forward control is re alized. the pwm ramp slope will change with the input voltage a utomatically compensating for changes in the input voltage. the input voltage can change due to variations in t he silver box output voltage or due to the wire and pcb-trace voltage drop related to changes in load current. gnd vout1 vosns1+ dacin vcc vdac1 vout1 iin1 vdrp1 lgnd ishare phsin vosns1- csin- csin+ gatel eain gateh sw vin fb1 eaout1 clkout clkin phsout pgnd vccl vcch dacin vcc clkin phsout csin+ gatel eain gateh ishare phsin sw pgnd vccl vcch csin- phsin phsout vid6 vid6 irosc vid6 vid6 vid6 vid6 vid6 vid6 vid6 vid6 gate drive voltage - + + + enable ramp discharge clamp body braking comparator ifb1 vdrp1 amp vdac clock generator current sense amplifier r s share adjust error amplifier reset dominant pwm latch error amplifier cout ir3514 control ic ir3505 phase ic output 1 only pwm comparator pwm comparator - + + + ramp discharge clamp enable body braking comparator share adjust error amplifier reset dominant pwm latch current sense amplifier r s ir3505 phase ic remote sense amplifier ccs rcs +- cfb1 rcs cbst + - ccs cbst + - + - ccp11 + - + - rfb12 rdrp1 cdrp1 rfb11 3k + - + - clk d q + - + - rcp1 + - 3k + - + - ccp12 clk d q + - figure 5 - pwm block diagram frequency and phase timing control the oscillator is located in the control ic and the system clock frequency is programmable from 250 kh z to 9 mhz by an external resistor. the control ic system cloc k signal (clkout) is connected to clkin of all the phase ics. the phase timing of the phase ics is controlled by the daisy chain loop, where control ic phase clock output (phsout) is connected to the phase clock input (phs in) of the first phase ic, and phsout of the first phase ic is connected to phsin of the second phase ic, etc. the last phase ic (phsout) is connected back to phsin of the control ic to complete the loop. during power up, t he control ic sends out clock signals from both clk out and phsout pins and detects the feedback at phsin pin t o determine the phase number and monitor any fault in the daisy chain loop. figure 6 shows the phase timing f or a four phase converter. downloaded from: http:///
ir3514 page 14 of 46 10/30/2007 phase ic1 pwm latch set control ic clkout (phase ic clkin) control ic phsout (phase ic1 phsin) phase ic 1 phsout (phase ic2 phsin) phase ic 2 phsout (phase ic3 phsin) phase ic 3 phsout (phase ic4 phsin) phase ic4 phsout (control ic phsin) figure 6 four phase oscillator waveforms pwm operation the pwm comparator is located in the phase ic. upon receiving the falling edge of a clock pulse, the p wm latch is set. this event starts the pwm ramp voltage charge cycle, turns off the low side driver, and turns on the high side driver after a non-overlap blank time. when the pwm ramp voltage exceeds the error amplifiers output voltage, the pwm latch is reset. this turns off the high side dr iver and then turns on the low side driver after th e non-overlap blank time; it activates the ramp discharge clamp, which quickly discharges the internal pwm ramp capa citor to the output voltage of share adjust amplifier in phase i c until the next clock pulse. the pwm latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nano seconds in response to a load step decrease. phases can overla p and go up to 100% duty cycle in response to a loa d step increase with turn-on gated by the clock pulses. an error amplifier output voltage greater than the co mmon mode input range of the pwm comparator results in 100% d uty cycle regardless of the voltage of the pwm ramp . this arrangement guarantees the error amplifier is alway s in control and can demand 0 to 100% duty cycle as required. it also favors response to a load step decrease whi ch is appropriate given the low output to input vol tage ratio of most systems. the inductor current will increase mu ch more rapidly than decrease in response to load t ransients. this control method is designed to provide single cycle transient response where the inductor curren t changes in response to load transients within a single switchi ng cycle maximizing the effectiveness of the power train and minimizing the output capacitor requirements. an additional advantage of the architecture is that differences in ground or input voltage at the phases have no effec t on operation since the pwm ramps are referenced t o vdac. figure 7 depicts pwm operating waveforms under vari ous conditions. downloaded from: http:///
ir3514 page 15 of 46 10/30/2007 phase ic clock pulse vdac eain pwmrmp gatel gateh duty cycle decrease due to vin increase (feed-forward) duty cycle increase due to load increase steady-state operation steady-state operation duty cycle decrease due to load decrease (body braking) or fault (vcc uv, ocp, vid fault) figure 7 pwm operating waveforms body braking tm in a conventional synchronous buck converter, the m inimum time required to reduce the current in the i nductor in response to a load step decrease is; o min max slew v i i l t ) (* the slew rate of the inductor current can be signif icantly increased by turning off the synchronous re ctifier in response to a load step decrease. the switch node v oltage is then forced to decrease until conduction of the synchronous rectifiers body diode occurs. this inc reases the voltage across the inductor from vout to vout + v bodydiode . the minimum time required to reduce the current in the inductor in response to a load transient decrease is now; bodydiode o min max slew v v i i l t ) (* since the voltage drop in the body diode is often h igher than output voltage, the inductor current sle w rate can be increased by 2x or more. this patent pending techni que is referred to as body braking and is accompl ished through the body braking comparator located in th e phase ic. if the error amplifiers output voltage drops below the vdac voltage or a programmable voltage, this co mparator turns off the low side gate driver. lossless average inductor current sensing inductor current can be sensed by connecting a seri es resistor and a capacitor network in parallel wit h the inductor and measuring the voltage across the capacitor, as shown in figure 8. the equation of the sensing netw ork is, cs cs l l cs cs l c c sr sl r si c sr s v s v 1 )( 1 1 )( )( . usually, the resistor r cs and capacitor c cs are chosen so that the time constant of r cs and c cs equals the time constant of the inductor which is the inductance l over the inductor dcr (r l ). if the two time constants match, the voltage across c cs is proportional to the current through l, and the sense circuit can be treated as if only a sense resistor with the value of r l was used. the mismatch of the time constants does not affect the measurement of inductor dc current, but does affects the ac compon ent of the inductor current. downloaded from: http:///
ir3514 page 16 of 46 10/30/2007 figure 8 inductor current sensing and current sen se amplifier the advantage of sensing the inductor current, vers us high side or low side sensing, is that the actua l output current being delivered to the load is obtained rather than sensing only a peak or sampled information about t he switch currents. the output voltage can be positioned to m eet a load line based on real time information. exc ept for a sense resistor in series with the inductor, this is the only sense method that can support a single cy cle transient response. other methods provide no information duri ng either load increase (low side sensing) or load decrease (high side sensing). an additional problem associated with peak or valle y current mode control for voltage positioning is t hat they suffer from peak-to-average errors. these errors will show in many ways but one example is the effect of freq uency variation. if the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. variations in inductance, current sense amplifier bandwidth, pwm prop delay, any added slope compensa tion, input voltage, and output voltage are all add itional sources of peak-to-average errors. current sense amplifier a high speed differential current sense amplifier i s located in the phase ic, as shown in figure 8. it s gain is nominally 32.5 at 25oc, and the 3850 ppm/oc increas e in inductor dcr should be compensated in the volt age loop feedback path. the current sense amplifier can accept positive dif ferential input up to 50mv and negative up to -10mv before clipping. the output of the current sense amplifier is summed with the dac voltage and sent to the con trol ic and other phases through an on-chip 3k ?uhvlvwrufrqqhfwhgwrwkh,6+$5(slq7kh,6+$5( slqvridoowkhskdvhvduh tied together and the voltage on the share bus repr esents the average current through all the inductor s and is used by the control ic for voltage positioning and curre nt limit protection. average current share loop current sharing between phases of the converter is achieved by the average current share loop in each phase ic. the output of the current sense amplifier is compar ed with average current at the share bus. if curren t in a phase is smaller than the average current, the share adjust amplifier of the phase will pull down the starting point of the pwm ramp thereby increasing its duty cycle and output c urrent; if current in a phase is larger than the av erage current, the share adjust amplifier of the phase will pull u p the starting point of the pwm ramp thereby decrea sing its duty cycle and output current. the current share amplifi er is internally compensated so that the crossover frequency of the current share loop is much slower than that of the voltage loop and the two loops do not interact. c o l r l r cs c cs v o current sense amp csout i l v l v cs c downloaded from: http:///
ir3514 page 17 of 46 10/30/2007 ir3514 theory of operation block diagram the block diagram of the ir3514 is shown in figure 3. the following discussions are applicable to eit her output plane unless otherwise specified. vid interface configuration the ir3514 hybrid control ic can operate in either svi (serial vid interface) or pvi (parallel vid int erface) mode. the state of vid1 upon enable assertion determines which mode the ir3514 will operate in; vid1=0v enab les the svi dual plane mode, conversely vid1=1 selects pv i single plane mode. svi mode has the ability to independently control b oth the vdd core and vddnb auxiliary planes require d by the cpu. the ir3514 can also receive power savings com mands through the svi serial bus and communicate th is information to the ir3507 or other phase ics with p si input capabilities. when operated in pvi (parallel vid interface) mode, the ir3514 controls the vdd core plane through 6 p arallel vid bits and the vddnb auxiliary plane power stage goes to high impedance. serial vid control (vid1=0 at enable assertion) the two serial vid interface (svid) pins svc and sv d are used to program the boot vid voltage upon ass ertion of enable while pwrok is de-asserted. see table 2 for the 2-bit boot vid codes. both vdac1 and vdac2 voltages will be programmed to the boot vid code un til pwrok is asserted. the boot vid code is stored by the ir3514 to be utilized again if pwrok is de-asserted . serial vid communication from the processor is enab led after the pwrok is asserted. addresses and dat a are serially transmitted in 8-bit words. the ir3514 ha s three fixed addresses to control vdac1, vdac2, or both vdac1 and vdac2 (see table 6 for addresses). the f irst data bit of the svid data word represents the psi bit which is passed on to the phase ics via the ir3514 psi_l pin. psi_l is pulled high by an internal 10k resistor to vccl when data bit 7 of an svid command is high. t he remaining data bits svid[6:0] select the desired vdacx regulation voltage as defined in table 3. svid[6:0 ] are the inputs to the digital-to-analog converter (dac) which then provides an analog reference voltage to the tr ansconductance type buffer amplifier. this vdacx bu ffer provides a system reference on the vdacx pin. the vdacx voltage along with error amplifier and remot e sense differential amplifier input offsets are post-packa ge trimmed to provide a 0.5% system set-point accuracy, as measured in figures 4a and 4b. vdacx slew rates ar e programmable by properly selecting external serie s rc compensation networks located between the vdacx and the lgnd pins. the vdacx source and sink currents are derived off the external oscillator frequency setti ng resistor, r rosc . the programmable slew rate enables the ir3514 to smoothly change the regulated output volt age throughout vid transitions resulting in a power supply input and output capacitor inrush currents, along with ou tput voltage overshoot, to be well controlled. the two serial vid interface (svid) pins svc and sv d can also program the vfix vid voltage upon assert ion of enable while pwrok is equal to vccl. see table 3 f or the 2-bit vfix vid codes. both vdac1 and vdac2 voltages will be programmed to the vfix code. the svc and svd pins require external pull-up biasing a nd should not be floated. bits description 7 psi_l: = 0 means the processor is at an optimal load for t he regulator(s) to enter power-saving mode. = 1 means the processor is not at an optimal load f or the regulator(s) to enter power-saving mode. 6:0 svid[6:0] as defined in table 4. table 1. serial vid 8-bit data field encoding downloaded from: http:///
ir3514 page 18 of 46 10/30/2007 table 2 C pre-pwrok 2 bit metal vid codes table 3 C vfix mode 2 bit vid code s svc svd output voltage(v) 0 0 1.1 0 1 1.0 1 0 0.9 1 1 0.8 table 4 - amd 7 bit svid codes svid [6:0] voltage (v) svid [6:0] voltage (v) svid [6:0] voltage (v) svid [6:0] voltage (v) 000_0000 1.5500 010_0000 1.1500 100_0000 0.7500 110 _0000 0.5000 000_0001 1.5375 010_0001 1.1375 100_0001 0.7375 110 _0001 0.5000 000_0010 1.5250 010_0010 1.1250 100_0010 0.7250 110 _0010 0.5000 000_0011 1.5125 010_0011 1.1125 100_0011 0.7125 110 _0011 0.5000 000_0100 1.5000 010_0100 1.1000 100_0100 0.7000 110 _0100 0.5000 000_0101 1.4875 010_0101 1.0875 100_0101 0.6875 110 _0101 0.5000 000_0110 1.4750 010_0110 1.0750 100_0110 0.6750 110 _0110 0.5000 000_0111 1.4625 010_0111 1.0625 100_0111 0.6625 110 _0110 0.5000 000_1000 1.4500 010_1000 1.0500 100_1000 0.6500 110 _1000 0.5000 000_1001 1.4375 010_1001 1.0375 100_1001 0.6375 110 _1001 0.5000 000_1010 1.4250 010_1010 1.0250 100_1010 0.6250 110 _1010 0.5000 000_1011 1.4125 010_1011 1.0125 100_1011 0.6125 110 _1011 0.5000 000_1100 1.4000 010_1100 1.0000 100_1100 0.6000 110 _1100 0.5000 000_1101 1.3875 010_1101 0.9875 100_1101 0.5875 110 _1101 0.5000 000_1110 1.3750 010_1110 0.9750 100_1110 0.5750 110 _1110 0.5000 000_1111 1.3625 010_1111 0.9625 100_1111 0.5625 110 _1111 0.5000 001_0000 1.3500 011_0000 0.9500 101_0000 0.5500 111 _0000 0.5000 001_0001 1.3375 011_0001 0.9375 101_0001 0.5375 111 _0001 0.5000 001_0010 1.3250 011_0010 0.9250 101_0010 0.5250 111 _0010 0.5000 001_0011 1.3125 011_0011 0.9125 101_0011 0.5125 111 _0011 0.5000 001_0100 1.3000 011_0100 0.9000 101_0100 0.5000 111 _0100 0.5000 001_0101 1.2875 011_0101 0.8875 101_0101 0.5000 111_0101 0.5000 001_0110 1.2750 011_0110 0.8750 101_0110 0.5000 111_0110 0.5000 001_0111 1.2625 011_0111 0.8625 101_0111 0.5000 111_0111 0.5000 001_1000 1.2500 011_1000 0.8500 101_1000 0.5000 111_1000 0.5000 001_1001 1.2375 011_1001 0.8375 101_1001 0.5000 111_1001 0.5000 001_1010 1.2250 011_1010 0.8250 101_1010 0.5000 111_1010 0.5000 001_1011 1.2125 011_1011 0.8125 101_1011 0.5000 111_1011 0.5000 001_1100 1.2000 011_1100 0.8000 101_1100 0.5000 111_1100 off 001_1101 1.1875 011_1101 0.7875 101_1101 0.5000 111_1101 off 001_1110 1.1750 011_1110 0.7750 101_1110 0.5000 111_1110 off 001_1111 1.1625 011_1111 0.7625 101_1111 0.5000 111_1111 off svc svd output voltage(v) 0 0 1.4 0 1 1.2 1 0 1.0 1 1 0.8 downloaded from: http:///
ir3514 page 19 of 46 10/30/2007 amd 6-bit parallel vid control (vid1=1 at enable assertion) pvi mode is enabled if vid1 is equal to logic 1 whe n enable is asserted. vid1 can then be used along with the other vidx bits to program vdac1 to amd 6-bit paral lel vid codes shown in table 5. output 2 is shut d own with vid2 defaulting to 0.5v, ss/del2 is held at 0v, and eaout2 = 0v which places all output 2 phase ics in high impedance mode. all output 2 fault and ovp communi cation to vrrdy, rosc and iin2 are disabled. pwrok and psi_l bits are ignored in pvi mode. pins vid0, vid1, vid4 and vid5 have 175 k ? resistors to lgnd and require external pull-up biasing. vid2/svd and vi d3/svc do not have internal resistor pull downs and also require external pull-up biasing. table 5 C amd 6-bit pvid table vid5 vid4 vid3 vid2 vid1 vid0 vout (v) vid5 vid4 vid3 vid2 vid1 vid0 vout(v) 0 0 0 0 0 0 1.5500 1 0 0 0 0 0 0.7625 0 0 0 0 0 1 1.5250 1 0 0 0 0 1 0.7500 0 0 0 0 1 0 1.5000 1 0 0 0 1 0 0.7375 0 0 0 0 1 1 1.4750 1 0 0 0 1 1 0.7250 0 0 0 1 0 0 1.4500 1 0 0 1 0 0 0.7125 0 0 0 1 0 1 1.4250 1 0 0 1 0 1 0.7000 0 0 0 1 1 0 1.4000 1 0 0 1 1 0 0.6875 0 0 0 1 1 1 1.3750 1 0 0 1 1 1 0.6750 0 0 1 0 0 0 1.3500 1 0 1 0 0 0 0.6625 0 0 1 0 0 1 1.3250 1 0 1 0 0 1 0.6500 0 0 1 0 1 0 1.3000 1 0 1 0 1 0 0.6375 0 0 1 0 1 1 1.2750 1 0 1 0 1 1 0.6250 0 0 1 1 0 0 1.2500 1 0 1 1 0 0 0.6125 0 0 1 1 0 1 1.2250 1 0 1 1 0 1 0.6000 0 0 1 1 1 0 1.2000 1 0 1 1 1 0 0.5875 0 0 1 1 1 1 1.1750 1 0 1 1 1 1 0.5750 0 1 0 0 0 0 1.1500 1 1 0 0 0 0 0.5625 0 1 0 0 0 1 1.1250 1 1 0 0 0 1 0.5500 0 1 0 0 1 0 1.1000 1 1 0 0 1 0 0.5375 0 1 0 0 1 1 1.0750 1 1 0 0 1 1 0.5250 0 1 0 1 0 0 1.0500 1 1 0 1 0 0 0.5125 0 1 0 1 0 1 1.0250 1 1 0 1 0 1 0.5000 0 1 0 1 1 0 1.0000 1 1 0 1 1 0 0.4875 0 1 0 1 1 1 0.9750 1 1 0 1 1 1 0.4750 0 1 1 0 0 0 0.9500 1 1 1 0 0 0 0.4625 0 1 1 0 0 1 0.9250 1 1 1 0 0 1 0.4500 0 1 1 0 1 0 0.9000 1 1 1 0 1 0 0.4375 0 1 1 0 1 1 0.8750 1 1 1 0 1 1 0.4250 0 1 1 1 0 0 0.8500 1 1 1 1 0 0 0.4125 0 1 1 1 0 1 0.8250 1 1 1 1 0 1 0.4000 0 1 1 1 1 0 0.8000 1 1 1 1 1 0 0.3875 0 1 1 1 1 1 0.7750 1 1 1 1 1 1 0.3750 downloaded from: http:///
ir3514 page 20 of 46 10/30/2007 output 1 (vdd) adaptive voltage positioning the ir3514 provides adaptive voltage positioning (a vp) on the output1 plane only. avp helps reduces t he peak to peak output voltage excursions during load trans ients and reduces load power dissipation at heavy l oad. the circuitry related to the voltage positioning is sho wn in figure 9. resistor r fb1 is connected between the error amplifiers inverting input pin fb1 and the remote s ense differential amplifier output, vout1. an inter nal current sink on the fb1 pin along with r fb1 provides programmability of a fixed offset voltage above the vdac1 voltage. the offset voltage generated across r fb1 forces the converters output voltage higher to ma intain a balance at the error amplifiers inputs. the fb1 sink current is derived by the external resistor r rosc that programs the oscillator frequency. the vdrp1 pin voltage is a buffered reproduction of the iin1 pin which is connected to the current sha re bus ishare. the voltage on ishare represents the syste m average inductor current information. at each ph ase ic, an rc network across the inductor provides current information which is gained up 32.5x and then added to the vdac x voltage. this phase current information is provide d on the ishare bus via a 3k resistor in the phase ics. output 1 inductor dcr temperature compensation a negative temperature coefficient (ntc) thermistor can be used for output1 inductor dcr temperature compensation. the thermistor should be placed close to the output1 inductors and connected in parallel with the feedback resistor, as shown in figure 10. the resis tor in series with the thermistor is used to reduce the nonlinearity of the thermistor. downloaded from: http:///
ir3514 page 21 of 46 10/30/2007 vosen1- csin- csin+ iin1 csin- eaout1 ishare vdrp1 phase ic phase ic ishare vout1 + - rfb1 current sense amplifier + - 3k 3k rdrp1 + - ... ... + - vdac vdac remote sense amplifier vdac1 vdac1 fb1 ifb current sense amplifier error amplifier vdrp amplifier control ic vosen1+ csin+ + - figure 9 adaptive voltage positioning + - eaout1 + - iin1 vdac1 ifb vdac1 control ic error amplifier rdrp1 vdrp amplifier vdrp1 rt rfb12 rfb11 fb1 vosen1+ vout1 vosen1- + - remote sense amplifier figure 10 temperature compensation of output1 ind uctor dcr downloaded from: http:///
ir3514 page 22 of 46 10/30/2007 remote voltage sensing vosenx+ and vosenx- are used for remote sensing and connected directly to the load. the remote sense differential amplifiers with high speed, low input offset and low input bias current ensure accurate v oltage sensing and fast transient response. start-up sequence the ir3514 has a programmable soft-start function t o limit the surge current during the converter star t-up. a capacitor connected between the ss/del x and lgnd pins controls soft start timing, over-cur rent protection delay and hiccup mode timing. constant current sources an d sinks control the charge and discharge rates of t he ss/del x . figure 11 depicts the svid start-up sequence. if th e enable input is asserted and there are no faults, the ss/del x pin will begin charging, the pre-pwrok 2 bit boot v id codes are read and stored, and both vdac pins tr ansition to the pre-pwrok boot vid code. the error amplifier ou tput eaout x is clamped low until ss/del x reaches 1.4v. the error amplifier will then regulate the converte rs output voltage to match the v(ss/del x )-1.4v offset until the converter output reaches the 2-bit boot vid code. t he ss/del x voltage continues to increase until it rises above the threshold of delay comparator where the vrrdy o utput is allowed to go high. the svid interface is activated upon pwrok assertion and the vdac x along with the converter output voltage will chang e in response to any svid commands. the pvi single plane mode start-up sequence is the same as the svid startup sequence with the exceptio ns that only ss/del1 will be allowed to charge and there is no boot vid voltage. pwrok is ignored. the error amplifier output eaoutx is clamped low un til ss/delx reaches 1.4v. the error amplifier will then regulate the converters output voltage to match th e ss/delx voltage less the 1.4v offset until the co nverter output reaches the pre-pwrok 2 bit metal vid code. the ss/ delx voltage continues to increase until it rises a bove the threshold of delay comparator. the vrrdy output is then de-asserted (allowed to go high). upon pwrok assertion the svid interface is activated and vdacx and converter output will change in response to an y svid commands. vccl under voltage, over current, or a low signal o n the enable input immediately sets the fault latch , which causes the eaout pin to drive low, thereby turning off the phase ic drivers. the vrrdy pin also drives low and ss/del x discharges to 0.2v. if the fault has cleared, the fault latch will be reset by the ss/del x discharge comparator allowing another soft start charge cycle to occur. other fault conditions, such as output over voltage , open vosns sense lines, or an open phase timing d aisy chain set a different group of fault latches that can onl y be reset by cycling vccl power. these faults dis charge ss/del x , pull down eaout x and drive vrrdy low. svid off codes turn off the converter by dischargin g ss/del x and pulling down eaoutx but do not drive vrrdy low. upon receipt of a non-off svid code the conver ter will re-soft start and transition to the voltag e represented by the svid code as shown in figure 11. the converter can be disabled by pulling the ss/del x pins below 0.6v. downloaded from: http:///
ir3514 page 23 of 46 10/30/2007 svid off transistion svid programmed voltage startup time svid transition vcc start delay (12v) ss/del 3.92v vrrdy vout 1.4v enable 4.0v vdacx normal operation 2-bit boot vid voltage svid set voltage eaout svid off command svid off command pwrok 2-bit boot vid on-hold 2-bit boot vid on-hold 0.5v svid on transistion svid on command svid on command 1.4v vid on the fly procession 0.8v svc svd 2-bit boot vid read & store 2-bit boot vid read & store svid transition figure 11 svid start-up sequence transitions downloaded from: http:///
ir3514 page 24 of 46 10/30/2007 serial vid interface protocol and vid-on-the-fly tr ansition the ir3514 supports the amd svi bus protocol and th e amd server and desktop svi wire protocol which is based on fast-mode i 2 c. svid commands from an amd processor are communi cated through svid bus pins svc and svd. the svc pin of the ir3514 does not have an op en drain output since amd svid protocol does not su pport slave clock stretching. the ir3514 transitions from a 2-bit boot vid mode t o svi mode upon assertion of pwrok. the smbus send byte protocol is used by the ir3514 vid-on-the-fly trans actions. the ir3514 will wait until it detects a s tart bit which is defined as an svd falling edge while svc is high. a 7bit address code plus one write bit (low) should then follow the start bit. this address code will be compared against an internal address table and the ir3514 wi ll reply with an acknowledge ack bit if the address is one of the th ree stored addresses otherwise the ack bit will not be sent out. the svd pin is pulled low by the ir3514 to generate the ack bit. table 6 has the list of addresses re cognized by the ir3514. the processor should then transmit the 8-bit data w ord immediately following the ack bit. data bit 7 is the psi_l bit which is followed by the 7bit amd code. the ir 3514 replies again with an ack bit once the data is received. if the received data is not a vid-off command, the ir3 514 immediately changes the dac analog outputs to t he new target. vdac1 and vdac2 then slew to the new vid v oltages. see figure 12a and 12b for a send byte ex amples. table 6 - svi send byte address table svi address [6:0] + wr description 110xx100b set vid only on output 1 110xx010b set vid only on output 2 110xx110b set vid on both output 1 and output 2 note: x in the above table 4 means the bit could be either 1 or 0. figure 12a send byte example downloaded from: http:///
ir3514 page 25 of 46 10/30/2007 figure 12b sending 1.55 vid to both outputs and tur ning off psi mode over-current hiccup protection after soft start the over current limit threshold is set by a resist or connected between ocsetx and vdacx pins. figure 13 shows the hiccup over-current protection with delay after vrrdy is asserted. the delay is required since ove r-current conditions can occur as part of normal operation du e to load transients or vid transitions. if the iinx pin voltage, which is proportional to t he average current plus vdacx voltage, exceeds the ocsetx voltage after vrrdy is asserted, it will initiate t he discharge of the capacitor at ss/delx through th e discharge current 47ua. if the over-current condition persist s long enough for the ss/delx capacitor to discharg e below the 120mv offset of the delay comparator, the fault lat ch will be set pulling the error amplifiers output low and inhibiting switching in the phase ics and de-asserting the vrr dy signal. the ss/del capacitor will then continue to discharge through the 4.5ua discharge current until it reaches 200 mv and the fault latch is reset all owing a normal soft start to occur. the output current is not cont rolled during the delay time. if an over-current co ndition is again encountered during the soft start cycle, the over-c urrent action will repeat and the converter will be in hiccup mode. downloaded from: http:///
ir3514 page 26 of 46 10/30/2007 over-current protection (output shorted) normal operation 3.88v ea hiccup over-current protection (output shorted) power-down ocp delay start-up with output shorted normal operation 3.92v ss/del iout vout vrrdy 1.4v enable ocp threshold 4.0v normal start-up (output shorted) normal start-up internal oc delay figure 13 hiccup over-current waveforms linear regulator output (vccl) the ir3514 has a built-in linear regulator contro ller, and only an external npn transistor is needed to create a linear regulator. the output voltage of the linear regulator can be programmed between 4.75v and 7.5v by the resistor divider at vcclfb pin. the regulator outpu t powers the gate drivers and other circuits of the phase ics along with circuits in the control ic, and the volt age is usually programmed to optimize the converter efficiency. the linear regulator can be compensated by a 4.7uf capa citor at the vccl pin. as with any linear regulator , due to stability reasons, there is an upper limit to the m aximum value of capacitor that can be used at this pin and its a function of the number of phases used in the multip hase architecture and their switching frequency. fi gure 14 shows the stability plots for the linear regulator with 5 phases switching at 750 khz. an external 5v can be connected to this pin to repl ace the linear regulator with appropriate selection of the vcclfb resistor divider, and vccldrv resistor. when using an external vccl, its essential to adjust it such that vcclfb is slightly less than the 1.19v reference voltage. this condition ensures that the vccldrv pin doesnt load the rosc pin. the switching frequency, fb1 bias current , vdac slew rate and ocset point are derived from t he loading current of rosc pin. figure 14 vccl regulator stability with 5 phases and phsout equals 750 khz downloaded from: http:///
ir3514 page 27 of 46 10/30/2007 vccl under voltage lockout (uvlo) the ir3514 has no under voltage lockout for convert er input voltage (vcc), but monitors the vccl volta ge instead, which is used for the gate drivers of phase ics and circuits in control ic and phase ics. during power up, the fault latch will be reset if vccl is above 94% of the vol tage set by resistor divider at vcclfb pin. if vccl voltage drops below 86% of the set value, the fault latch will be set. vid off codes svid off codes of 111_1100, 111_1101, 111_1110, and 111_1111 turn off the converter by pulling down ea outx voltage and discharging ss/delx through the dischar ge current 47ua, but do not drive vrrdy low. upon r eceipt of a non-off svid code the converter will turn on and transition to the voltage represented by the svid a s shown in figure 11. voltage regulator ready (vrrdy) the vrrdy pin is an open-collector output and shoul d have an external pull-up resistor. during soft st art, vrrdy remains low until the output voltage is in regulati on and ss/del x is above 3.9v. the vrrdy pin becomes low if enable is low, vccl is below 86% of target, an over current condition occurs for at least 1024 phsout clocks prior to vrrdy, an over current condition occurs af ter vrrdy and ss/del x discharges to the delay threshold, an open phase timing daisy chain condition occurs, vos ns lines are detected open, vout x is 315mv below vdac x , or if the error amp is sensed as operating open loo p for 8 phsout cycles. a high level at the vrrdy pi n indicates that the converter is in operation with no fault an d ensures the output voltage is within the regulati on. output 2 can not affect vrrdy in pvi mode. vrrdy monitors the output voltage. if any of the vo ltage planes fall out of regulation, vrrdy will bec ome low, but the vr continues to regulate its output voltages. t he pwrok input may or may not de-assert prior to th e voltage planes falling out of specification. output voltage out of spec is defined as 315mv to 275mv below nom inal voltage. vid on-the-fly transition which is a voltage plane transitioning between one voltage associated with o ne vid code and a voltage associated with another vid code is n ot considered to be out of specification. a pwrok de-assert while enable is high results in a ll planes regulating to the previously stored 2-bit boot vid. if the 2-bit boot vid is higher than the vid prior to pwrok de-assertion, this transition will not be tre ated as vid on- the-fly and if either of the two outputs is out of spec high, vrrdy will be pulled down. open voltage loop detection the output voltage range of error amplifier is cont inuously monitored to ensure the voltage loop is in regulation. if any fault condition forces the error amplifier outp ut above vccl-1.08v for 8 phsout switching cycles, the fault latch is set. the fault latch can only be cleared b y cycling the power to vccl. load current indicator output the vdrp pin voltage represents the average current of the converter plus the dac voltage. the load cu rrent information can be retrieved by using a differentia l amplifier to subtract vdac1 voltage from the vdrp 1 voltage. enable input pulling the enable pin below 0.8v sets the fault la tch. forcing enable to a voltage above 1.94v resul ts in the pre-pwrok 2 bit vid codes off the svd and svc pins to be read and stored. ss/del x pins are also allowed to begin their power-up cycles. downloaded from: http:///
ir3514 page 28 of 46 10/30/2007 over voltage protection (ovp) output over-voltage might occur due to a high side mosfet short or if the output voltage sense path is compromised. if the over-voltage protection compara tors sense that either vout x pin voltage exceeds vdac x by 125mv, the over voltage fault latch is set which pu lls the error amplifier output low to turn off the converter power stage. the ir3514 communicates an ovp condition to the system by raising the rosc/ovp pin voltage to w ithin v(vccl) C 1.2v. an ovp condition is also communica ted to the phase ics by forcing the iin pin (which is tied to the ishare bus and ishare pins of the phase ics) to vccl as shown in figure 15. in each phase ic, the ovp circuit overrides the normal pwm operation to ensur e the low side mosfet turn-on within approximately 150ns. the low side mosfet will remain on until the ishare pins fall below v(vccl) - 800mv. an over voltage fault condition is latched in the ir3514 and can only be cleared by cycling the power to vccl. output 2 ovp is disabled in pvi mode. during dynamic vid down at light to no load, false ovp triggering is prevented by increasing the ovp t hreshold to a fixed 1.6v whenever a dynamic vid is detected and t he difference between output voltage and the fast i nternal vdac is more than 50mv, as shown in figure 16. the over-voltage threshold is changed back to vdac+125m v if the difference between output voltage and the fast internal vdac is less than 50mv. the overall system must be considered when designin g for ovp. in many cases the over-current protectio n of the ac-dc or dc-dc converter supplying the multiphase c onverter will be triggered thus providing effective protection without damage as long as all pcb traces and compon ents are sized to handle the worst-case maximum cur rent. if this is not possible, a fuse can be added in the in put supply to the multiphase converter. after ovp fault latch output voltage (vout) ovp threshold iin (phase ic ishare) vccl-800 mv ovp condition normal operation gateh (phase ic) gatel (phase ic) error amplifier output (eaout) vdac figure 15 - over-voltage protection during normal o peration downloaded from: http:///
ir3514 page 29 of 46 10/30/2007 output voltage (vo) vid down normal operation vdac vid ov threshold vdac + 125mv 1.6v normal operation vid up low vid vdac 50mv 50mv figure 16 over-voltage protection during dynamic vi d open remote sense line protection if either remote sense line vosen x + or vosen x - is open, the output of remote sense amplifier (vo ut x ) drops. the ir3514 continuously monitors the vout x pin and if vout x is lower than 200 mv, two separate pulse currents are applied to the vosen x + and vosen x - pins to check if the sense lines are open. if vos en x + is open, a voltage higher than 90% of v(vccl) will be present at vosen x + pin and the output of open line detect comparator will be high. if vosen x - is open, a voltage higher than 400mv will be pres ent at vosen x - pin and the open line detect comparator output will be high. with either sense line open, the open sense line fault latch wi ll be set to force the error amplifier output low and immediatel y shut down the converter. ss/del x will be discharged and the open sense fault latch can only be reset by cycling the power to vccl. open daisy chain protection ir3514 checks the daisy chain every time it powers up. it starts a daisy chain pulse on the phsout pin and detects the feedback at phsin pin. if no pulse come s back after 32 clkout pulses, the pulse is restart ed again. if the pulse fails to come back the second time, the o pen daisy chain fault is registered, and ss/del is not allowed to charge. the fault latch can only be reset by cyclin g the power to vccl. after powering up, the ir3514 monitors phsin pin fo r a phase input pulse equal or less than the number of phases detected. if phsin pulse does not return within the number of phases in the converter, another pulse i s started on phsout pin. if the second started phsout pulse does not return on phsin, an open daisy chain fault is registered. phase number determination after a daisy chain pulse is started, the ir3514 ch ecks the timing of the input pulse at phsin pin to determine the phase number. downloaded from: http:///
ir3514 page 30 of 46 10/30/2007 applications information css/del2 ishare2 cvdac2 rvdac2 vcc 16 sw 15 gateh 14 nc3 20 phsin 5 vccl 12 pgnd 9 dacin 3 phsout 7 gatel 10 nc1 6 psi 2 iout 1 lgnd 4 clkin 8 boost 13 csin+ 17 csin- 18 eain 19 nc2 11 u31 ir3507 vid0 vddnbsen- ccp22 ccp21 rcp2 vcc 16 sw 15 gateh 14 nc3 20 phsin 5 vccl 12 pgnd 9 dacin 3 phsout 7 gatel 10 nc1 6 psi 2 iout 1 lgnd 4 clkin 8 boost 13 csin+ 17 csin- 18 eain 19 nc2 11 u61 ir3507 vdd 5-phase converter vddnb converter cin5 rdrp11 l5 q12 cvcc2 q22 u32 u51 ccs2 css/del1 cin4 rfb13 ccs1 phsout cvccl rcs5 cvccl4 l2 cfb1 cvccl6 l1 rdrp12 rcs4 cbst1 q62 cvcc6 vid4 q41 rcs1 cvcc5 cvccl3 rfb12 u52 cbst61 rcp1 ccs6 ccp12 q42 vcc 16 sw 15 gateh 14 nc3 20 phsin 5 vccl 12 pgnd 9 dacin 3 phsout 7 gatel 10 nc1 6 psi 2 iout 1 lgnd 4 clkin 8 boost 13 csin+ 17 csin- 18 eain 19 nc2 11 u21 ir3507 q21 rocset1 ccs4 cbst4 cvccl1 cin6 rvccldrv v2ea cvccl2 cin1 cvcc4 q11 cin3 u31 cin2 cbst3 rcs6 rvcclfb2 q61 ccs5 l3 l4 vdac ccs3 cvcc3 rosc cvcc1 cvccl5 rvdac1 cdrp1 rvcclfb1 q1 cvdac1 ccp11 cbst5 l6 rfb11 cbst3 rtherm1 rcs3 rcs2 12v svd/vid2 svc/vid3 pwrok vddpwrgd cfb2 rfb21 rfb22 vid0 1 vid5 2 vid4 3 pwrok 4 enable 5 iin2 6 ssdel2 7 vdac2 8 ocset2 9 eaout2 10 nc1 11 fb2 12 vout2 13 wosen2+ 14 vosen2- 15 vosen1- 16 vosen1+ 17 vout1 18 fb1 19 nc2 20 eaout1 21 ocset1 22 vdac1 23 ssdel1 24 iin1 25 vdrp1 26 rosc/ovp 27 psi_l 28 lgnd 29 nc3 30 vid1 40 svd/vid2 39 svc/vid3 38 vrrdy 37 vccldrv 36 vcclfb 35 vccl 34 phsin 33 phsout 32 clkout 31 pad 41 ir3514 u1 enable vcc 16 sw 15 gateh 14 nc3 20 phsin 5 vccl 12 pgnd 9 dacin 3 phsout 7 gatel 10 nc1 6 psi 2 iout 1 lgnd 4 clkin 8 boost 13 csin+ 17 csin- 18 eain 19 nc2 11 u11 ir3507 vdd+ vdd sense+ vdd sense- vdd- vddsen+ vddsen- cout vcc 16 sw 15 gateh 14 nc3 20 phsin 5 vccl 12 pgnd 9 dacin 3 phsout 7 gatel 10 nc1 6 psi 2 iout 1 lgnd 4 clkin 8 boost 13 csin+ 17 csin- 18 eain 19 nc2 11 u41 ir3507 vddnb+ vddnb sense+ vddnb sense- vddnb- vddnbsen+ vddnbsen- coutnb phsin vcc 16 sw 15 gateh 14 nc3 20 phsin 5 vccl 12 pgnd 9 dacin 3 phsout 7 gatel 10 nc1 6 psi 2 iout 1 lgnd 4 clkin 8 boost 13 csin+ 17 csin- 18 eain 19 nc2 11 u51 ir3507 vddsen- vddsen+ v2ea vdac2 rocset2 vddea clkout vgate vddnbsen+ vid5 close to power stage vid0 figure 17 ir3514 \ ir3507 five phases C one phase d ual outputs converter downloaded from: http:///
ir3514 page 31 of 46 10/30/2007 design procedures - ir3514 and ir3505 chipset ir3514 external components all the output components are selected using one ou tput but suitable for both unless otherwise specifi ed. oscillator resistor r r osc the ir3514 generates square wave pulses to synchron ize the phase ics. the switching frequency of the e ach phase converter equals the phsout frequency, which is set by the external resistor r rosc (use figure 2 to determine the r rosc value). the clkout frequency equals the switching f requency multiplied by the phase number. soft start capacitor c ss/del the soft start capacitor c ss/del programs four different time parameters, soft star t delay time, soft start time, vr ready delay time and over-current fault latch delay time after vr ready. ss/del pin voltage controls the slew rate of the co nverter output voltage, as shown in figure 11. once the enable pin rises above 1.65v, there is a soft-start delay time td1 during which ss/del pin is charged from zero to 1.4 v. once ss/del reaches 1.4 v, the error amplifier output is released to begin soft start. the soft start time, td2, represents the time during which convert er voltage rises from zero to pre-pwrok vid voltage and the ss/del pin voltage rises from 1.4 v to pre-pwrok vi d voltage plus 1.4 v. vr-ready delay time, td3, is the time period between where vr reaches pre-pwrok vid volta ge and vr-ready signal assertion. calculate c ss/del based on the required soft start time td2. pwrok pre pwrok pre chg del ss v td v i td c ? ? ? 6 / 10 * 50 *2 *2 (1) the soft start delay time td1 and vr ready delay ti me td3 are determined by equation (2) and (3) respe ctively. 6 / / 10 * 50 4.1* 4.1* 1 ? del ss chg del ss c i c td (2) 6 / / 10 * 50 )4.1 92.3(* )4.1 92.3(* 3 ? ? ? pwrok pre del ss chg pwrok pre del ss v c i v c td (3) once c ss/del is chosen, use equation (4) to calculate the maxim um over-current fault latch delay time t ocdel. 6 / / 10 * 47 12.0* *5.2 12.0* *5.2 ? del ss dischg del ss ocdel c i c t (4) due to the exponential turn-on slope of the dischar ge current (47ua), a correction factor (x2.5) is ad ded to the equation (4) to accurately predict over-current del ay time. vdac slew rate programming capacitor c vdac and resistor r vdac the slew rate of vdac down-slope sr down can be programmed by the external capacitor c vdac as defined in (5), where i sink is the sink current of vdac pin. the slew rate of v dac up-slope is three times greater that of down-slope. the resistor r vdac is used to compensate vdac circuit and is determin ed by (6). downloaded from: http:///
ir3514 page 32 of 46 10/30/2007 down sink vdac sr i c (5) 2 15 10 2.3 5.0 vdac vdac c r ? (6) over current setting resistor r ocset the inductor dc resistance is utilized to sense the inductor current. the copper wire of inductor has a constant temperature coefficient of 3850 ppm/c, and therefo re the maximum inductor dcr can be calculated from (7), where r l_max and r l_room are the inductor dcr at maximum temperature t l_max and room temperature t l _ room respectively. )] ( 10* 3850 1[ _ _ 6 _ _ room l max l room l max l t t r r ? (7) the total input offset voltage (v cs_tofst ), of current sense amplifier in phase ics, is the sum of input offset (v cs_ofst) of the amplifier itself and that created by the am plifier input bias current flowing through the curr ent sense resistor r cs . cs csin ofst cs tofst cs r i v v ? _ _ (8) the over current limit is set by the external resis tor r ocset as defined in (9). i limit is the required over current limit. i ocset is the bias current of ocset pin and can be calcul ated with the equation in the electrical characteristics table. g cs is the gain of the current sense amplifier. k p is the ratio of inductor peak current over average current in each phase and can be calcu lated from (10). ocset cs tofst cs p max l limit ocset i g v k r n i r / ] ) 1( [ _ _ (9) n i f v l v v v k o sw i o o i p / )2 /( ) ( (10) vccl programming resistor r vcclfb1 and r vcclfb2 since vccl voltage is proportional to the mosfet ga te driver loss and inversely proportional to the mosfet conduction loss, the optimum voltage should be chosen to maximize the converter efficiency. vcc l linear regulator consists of an external npn transi stor, a ceramic capacitor and a programmable resist or divider. pre-select r vcclfb1 , and calculate r vcclfb2 from (11). 23.1 23.1* 1 2 vccl r r vcclfb vcclfb (11) no load offset setting resistor rfb11, rfb13, rtherm1 and adaptive voltage positioning resistor rdrp11 for output1 define r fb_r is the effective offset resistor at room temperatur e equals to r fb11 //(r fb13 +r therm1 ). given the offset voltage v o_nlofst above the dac voltage, calculate the sink current f rom the fb1 pin i fb1 using the equation in the electrical characteristics table, t hen the effective offset resistor value r fb1 can be determined from (12). downloaded from: http:///
ir3514 page 33 of 46 10/30/2007 1 _ _ fb nlofst o r fb i v r (12) adaptive voltage positioning lowers the converter v oltage by r o *i o, where r o is the required output impedance of the converter. pre-select feedback resistor r fb, and calculate the droop resistor rdrp, o cs room l r fb drp r n g r r r * _ _ 11 (13) calculate the desired effective feedback resistor a t the maximum temperature r fb_m using (14) max l cs o drp m fb r g n r r r _ 11 _ * (14) a negative temperature constant (ntc) thermistor r therm1 is required to sense the temperature of the power stage for the inductor dcr thermal compensation. pr e-select r therm, r therm1 must be bigger than r fb_r and r tmax1 - ntc thermistor resistance at allowed maximum temper ature t max must be bigger than r fb_m, r tmax1 is calculated from (15). )] 1 1 (* [ * _ _ 1 1 1 room max l therm therm tmax t t b exp r r (15) select the series resistor r fb13 using (16) to linearize the ntc thermistor, which h as non-linear characteristics in the operational temperature range. 2 )) /( * *) ( * (*4 ) ( _ _ _ _ 1 1 1 1 2 1 1 13 r fb m fb m fb r fb tmax therm tmax therm tmax therm fb r r r r r r r r r r r (16) use equation (17) to determine r fb11 1 13 _ 11 1 1 1 therm fb r fb fb r r r r (17) downloaded from: http:///
ir3514 page 34 of 46 10/30/2007 ir3505 external components inductor current sensing capacitor c cs and resistor r cs the dc resistance of the inductor is utilized to se nse the inductor current. usually the resistor r cs and capacitor c cs in parallel with the inductor are chosen to match the time constant of the inductor, and therefore th e voltage across the capacitor c cs represents the inductor current. if the two time c onstants are not the same, the ac component of the capacitor voltage is different fro m that of the real inductor current. the time const ant mismatch does not affect the average current sharing among t he multiple phases, but affect the current signal i share as well as the output voltage during the load current transient if adaptive voltage positioning is adopte d. measure the inductance l and the inductor dc resist ance r l . pre-select the capacitor c cs and calculate r cs as follows. cs l cs c rl r (21) bootstrap capacitor c bst depending on the duty cycle and gate drive current of the phase ic, a capacitor in the range of 0.1uf to 1uf is needed for the bootstrap circuit. decoupling capacitors for phase ic 0.1uf-1uf decoupling capacitors are required at vcc and vccl pins of phase ics. downloaded from: http:///
ir3514 page 35 of 46 10/30/2007 voltage loop compensation the adaptive voltage positioning (avp) is usually a dopted in the computer applications to improve the transient response and reduce the power loss at heavy load. l ike current mode control, the adaptive voltage posi tioning loop introduces extra zero to the voltage loop and splits the double poles of the power stage, which m ake the voltage loop compensation much easier. adaptive voltage positioning lowers the converter v oltage by r o *i o, where r o is the required output impedance of the converter. the selection of compensation types depends on the output capacitors used in the converter. for the ap plications using electrolytic, polymer or al-polymer capacitor s and running at lower frequency, type ii compensat ion shown in figure 18(a) is usually enough. while for the ap plications using only ceramic capacitors and runnin g at higher frequency, type iii compensation shown in figure 18 (b) is preferred. for applications where avp is not required, the com pensation is the same as for the regular voltage mo de control. for converter using polymer, al-polymer, a nd ceramic capacitors, which have much higher esr z ero frequency, type iii compensation is required as sho wn in figure 18(b) with r drp and c drp removed. rcp ccp1 eaout ccp rfb rdrp vo+ vdrp vdac + - eaout fbfb cfb cdrp rcp eaout ccp1 ccp rfb rdrp vo+ vdrp vdac fb + - eaout rfb1 (a) type ii compensation (b) type iii compensation figure 18. voltage loop compensation network type ii compensation for avp applications determine the compensation at no load, the worst ca se condition. choose the crossover frequency fc bet ween 1/10 and 1/5 of the switching frequency per phase. assume the time constant of the resistor and capaci tor across the output inductors matches that of the inductor, and determine r cp and c cp from (23) and (24), where l e and c e are the equivalent inductance of output inductors and the equivalent capacitance of output capacitors respectively. 2 2 ) * * * 2( 1 * 5 ) 2( c c i fb e e c cp r c f v r c l f r s s (23) cp e e cp r c l c 10 (24) c cp1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. a ceramic capacitor between 10pf and 220pf is usual ly enough. downloaded from: http:///
ir3514 page 36 of 46 10/30/2007 type iii compensation for avp applications determine the compensation at no load, the worst ca se condition. assume the time constant of the resis tor and capacitor across the output inductors matches that of the inductor, the crossover frequency and phase margin of the voltage loop can be estimated by (25) and (26), where r le is the equivalent resistance of inductor dcr. le fb cs e drp c r r g c r f * * 2 1 s (25) s t 180 )5.0 tan( 90 1 a c (26) choose the desired crossover frequency fc around fc 1 estimated by (25) or choose fc between 1/10 and 1 /5 of the switching frequency per phase, and select the c omponents to ensure the slope of close loop gain is -20db /dec around the crossover frequency. choose resisto r r fb1 according to (27), and determine c fb and c drp from (28) and (29). fb fb r r 2 1 1 to fb fb r r 3 2 1 (27) 1 4 1 fb c fb r f c s (28) drp fb fb fb drp r c r r c ) ( 1 (29) r cp and c cp have limited effect on the crossover frequency, an d are used only to fine tune the crossover frequency and transient load response. determine r cp and c cp from (30) and (31). i fb e e c cp v r c l f r 5 ) 2( 2 s (30) cp e e cp r c l c 10 (31) c cp1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. a ceramic capacitor between 10pf and 220pf is usual ly enough. type iii compensation for non-avp applications resistor r drp and capacitor c drp are not needed. choose the crossover frequency fc between 1/10 and 1/5 of wkh vzlwfklqj iuhtxhqf\ shu skdvh dqg vhohfw wkh gh vluhg skdvh pdujlq f &dofxodwh . idfwru iurp dqg determine the component values based on (33) to (37 ), )]5.1 180 ( 4 tan[ c k t s (32) k v f c l r r i c e e fb cp 5 ) 2( 2 s (33) cp c cp r f k c s 2 (34) cp c cp r k f c s 2 1 1 (35) downloaded from: http:///
ir3514 page 37 of 46 10/30/2007 fb c fb r f k c s 2 (36) fb c fb c k f r s 2 1 1 (37) current share loop compensation the internal compensation of current share loop ens ures that crossover frequency of the current share loop is at least one decade lower than that of the voltage loo p so that the interaction between the two loops is eliminated. downloaded from: http:///
ir3514 page 38 of 46 10/30/2007 design example C amd five - one phase due output co nverter (figure 17) specifications input voltage: v i =12 v dac voltage: v dac =1.2 v no load output voltage offset for output1: v o_nlofst =15 mv output1 current: i o1 =95 adc output2 current: i o1 =20 adc maximum output1 current: i omax1 =120 adc maximum output1 current: i omax2 = 26 adc output impedance: r o =0.32 m ? dynamic vid slew rate: sr=3.25mv/us over temperature threshold: t max =115 oc power stage phase number: n1=6, n2=1 switching frequency: f sw =550 khz output inductors: l1=120 nh, l2=220 nh, r l = 0.5m ? output capacitors: poscaps, c=470uf, r c = 8m ?1xpehu& n1=9, cn2=5 ir3514 external components oscillator resistor rosc once the switching frequency is chosen, r osc can be determined from the equation in the electrical characteristics table. for switching frequency of 5 00khz per phase, choose r osc =23.2k ? soft start capacitor c ss/del determine the soft start capacitor from the require d soft start time. uf vboot i td c chg del ss 1.0 0 . 1 10 * 50 * 10 *2 *2 6 3 / ? ? the soft start delay time is ms i c td chg del ss 2.2 10 * 50 1.1* 10 *1.0 1.1* 1 6 6 / ? ? the vr ready delay time is ms i v c td chg boot del ss 6.3 10 * 62 )1.1 1 92.3(* 10 *1.0 )1.1 92.3(* 3 6 6 / ? ? the maximum over current fault latch delay time is ms i c t dischg del ss ocdel 638 .0 10 * 62 12.0* 10 *1.0 *5.2 12.0* *5.2 6 6 / ? ? downloaded from: http:///
ir3514 page 39 of 46 10/30/2007 vdac slew rate programming capacitor c vdac and resistor r vdac nf sr i c down sink vdac 1.14 10*2.3 10 2.45 3 6 ? , choose c vdac =22nf ohm c r vdac vdac 1.7 10 2.3 5.0 2 15 ? over current setting resistor r ocset the output1 over current limit is 115a and the outp ut2 over current limit is 25a. from the electrical characteristics table can get the bias current of ocset pin (i ocset ) is 26ua with r osc =23.2 k ? 7kh wrwdo fxuuhqw vhqvh amplifier input offset voltage is around 0mv, calcu late constant k p, the ratio of inductor peak current over average current in each phase, 38.0 5/ 115 )2 10* 520 12 10* 120 /(2.1)2.1 12( / )2 /( ) ( 1 3 9 ? n i f v l v v v k limit sw i o o i p 19.0 25 )2 10* 520 12 10* 220 /(2.1)2.1 12( 2 3 9 ? p k ocset cs tofst cs p l limit ocset i g v k r n i r / ] ) 1( [ 1 _ : ? ? k 6.21 ) 10*26 /( 34*)38.1 10*52.0 5 115 ( 6 3 ocset cs tofst cs p l limit ocset i g v k r n i r / ] ) 1( [ 2 _ : k 4.18 ) 10*26 /( 34*)19.1 10*47.0 1 25 ( 6 3 vccl programming resistor r vcclfb1 and r vcclfb2 choose vccl=7v to maximize the converter efficiency . pre-select r vcclfb1 n dqgfdofxodwh5 vcclfb2. : k vccl r r vcclfb vcclfb 26.4 23.1 7 23.1* 10*20 23.1 23.1* 3 1 2 no load offset setting resistor rfb11, rfb13, rtherm1 and adaptive voltage positioning resistor rdrp11 for output1 define r fb_r is the effective offset resistor at room temperatur e equals to r fb11 //(r fb13 +r therm1 ). given the offset voltage v o_nlofst above the dac voltage, calculate the sink current f rom the fb1 pin i fb1 = 26ua using the equation in the electrical characteristics tabl e, then the effective offset resistor value r fb_r 1 can be determined by: ohm i v r fb nlofst o r fb 577 10*26 10*15 1 6 3 1 _ _ ? ? adaptive voltage positioning lowers the converter v oltage by r o *i o, where r o is the required output impedance of the converter. pre-select feedback resistor r fb, and calculate the droop resistor rdrp, downloaded from: http:///
ir3514 page 40 of 46 10/30/2007 kohm r n g r r r o cs room l r fb drp 7.6 10*3.0*5 34* 10*52.0* 577 * 1 3 3 _ _ ? ? in the case of thermal compensation is required, us e equation (14) to (17) to select the r fb network resistors. ir3505 external components inductor current sensing capacitor c cs and resistor r cs choose c cs 1=c cs 2=0.1uf, and calculate r cs, : ? ? ? k c rl r cs l cs 3.2 10*1.0 ) 10*52.0/( 10* 120 1 6 3 9 downloaded from: http:///
ir3514 page 41 of 46 10/30/2007 layout guidelines the following layout guidelines are recommended to reduce the parasitic inductance and resistance of t he pcb layout, therefore minimizing the noise coupled to t he ic. x dedicate at least one middle layer for a ground pl ane lgnd. x connect the ground tab under the control ic to lgn d plane through a via. x separate analog bus (eaoutx, vdacx and iinx) from digital bus (clkin, phsin, and phsout) to reduce the noise coupling. x place vccl decoupling capacitor cvccl as close as possible to vccl and lgnd pins. x place the following critical components on the sam e layer as control ic and position them as close as possible to the respective pins, rosc, rocsetx, rvd acx, cvdacx, and css/delx. avoid using any via for the connection. x place the compensation components on the same laye r as control ic and position them as close as possi ble to eaoutx, fbx, voutx and vdrp1 pins. avoid using a ny via for the connection. x use kelvin connections for the remote voltage sens e signals, vosnsx+ and vosnsx-, and avoid crossing over the fast transition nodes, i.e. switching node s, gate drive signals and bootstrap nodes. x avoid analog control bus signals, vdacx, iinx, and especially eaoutx, crossing over the fast transiti on nodes. x separate digital bus, clkout, phsout and phsin fro m the analog control bus and other compensation components. downloaded from: http:///
ir3514 page 42 of 46 10/30/2007 pcb metal and component placement x lead land width should be equal to nominal part le ad width. the minimum lead to lead spacing should be ?ppwrplqlpl]hvkruwlqj x lead land length should be equal to maximum part l ead length + 0.3 mm outboard extension + 0.05mm inboard extension. the outboard extension ensures a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment an d ensure a fillet. x center pad land length and width should be equal t o maximum part pad length and width. however, the minimum metal to metal spacing should be ?ppirur]&rsshu?ppirur]&rsshu dqg? 0.23mm for 3 oz. copper) x a single 0.30mm diameter via shall be placed in th e center of the pad land and connected to ground to minimize the noise effect on the ic. downloaded from: http:///
ir3514 page 43 of 46 10/30/2007 solder resist x the solder resist should be pulled away from the m etal lead lands by a minimum of 0.06mm. the solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all non solder mask defined (nsmd). therefore pulling the s/r 0.06mm will always ensure nsmd pads. x the minimum solder resist width is 0.13mm. x at the inside corner of the solder resist where th e lead land groups meet, it is recommended to provi de a fillet so a solder resist width of ?ppuhpdlqv x the land pad should be solder mask defined (smd), with a minimum overlap of the solder resist onto the copper of 0.06mm to accommodate solder resist m is-alignment. in 0.5mm pitch cases it is allowable to have the solder resist opening for the land pad to be smaller than the part pad. x ensure that the solder resist in-between the lead lands and the pad land is ? ppgx e to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. x the single via in the land pad should be tented or plugged from bottom boardside with solder resist. downloaded from: http:///
ir3514 page 44 of 46 10/30/2007 stencil design x the stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. reducing the amount of solder deposited will minimi ze the occurrence of lead shorts. since for 0.5mm pitch devices the leads are only 0.25mm wide, the s tencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. x the stencil lead land apertures should therefore b e shortened in length by 80% and centered on the le ad land. x the land pad aperture should be striped with 0.25m m wide openings and spaces to deposit approximately 50% area of solder on the center pad. if too much solder is deposited on the center pad the part will float and the lead lands will be open . x the maximum length and width of the land pad stenc il aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decreas e the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. downloaded from: http:///
ir3514 page 45 of 46 10/30/2007 package information 40l mlpq (6 x 6 mm body) ja = 18 o &: jc = 0.5 o c/w data and specifications subject to change without n otice. this product has been designed and qualified for th e consumer market. qualification standards can be found on irs web si te. ir world headquarters: 233 kansas st., el segundo, california 90245, usa t el: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact informati on . downloaded from: http:///
ir3514 page 46 of 46 10/30/2007 www.irf.com downloaded from: http:///

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